|Paper title||:||Comparison Study of 1- bit Full Adder Design using Different Technologies|
|Affiliation||:||NIET Greater Noida, India|
|Paper Abstract||:||The adder is an important unit in any processor and controller circuit. There are so many full adder circuits which have been proposed and designed. In this proposed work a 1-bit hybrid full adder circuit using Complementary Pass Transistor Logic and Transmission Gate Logic is designed and then compared with the existing designs such as C-CMOS, CPL,24-T full adder, TGL, Transmission Function Adder and hybrid full adder using C-CMOS and TGL logic designs. Comparative descriptions of various parameters like propagation delay, power consumption and Power Delay Product have been done. The result shows that delay is reduced by 68.037%, average power reduced by 18.90% and PDP is reduced by 12.84%.|
|Conference Details||:||IRF International Conference,NEW DELHI,16TH December,2016|
INTER. CONF. ON RECENT INNOVATIONS IN ENGINEERING AND TECHNOLOGY (ICRIET-2017),JaipurView Detail
INTERNATIONAL CONFERENCE ON SCIENCE, TECHNOLOGY ,ENGINEERING AND MANAGEMENT (ICSTEM-2017)View Detail
International Conference on Knowledge, Information, Technology and Sciences - (ICKITS-2016)View Detail
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